| Rule Violations |
Count |
| Clearance Constraint (Gap=0.152mm) (TouchesRoom('FETs1') OR TouchesRoom('FETs2')),(All) |
0 |
| Clearance Constraint (Gap=0.711mm) (InNetClass('EMI-Clearance')),(All) |
0 |
| Clearance Constraint (Gap=0.198mm) (All),(All) |
0 |
| Clearance Constraint (Gap=0mm) (IsPad),(OnLayer('Keep-Out Layer')) |
0 |
| Clearance Constraint (Gap=0.152mm) (TouchesRoom('IC')),(All) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
0 |
| Modified Polygon (Allow modified: No), (Allow shelved: No) |
0 |
| Width Constraint (Min=0.2mm) (Max=2mm) (Preferred=0.25mm) (All) |
0 |
| Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) |
0 |
| Hole Size Constraint (Min=0.025mm) (Max=5.4mm) (All) |
0 |
| Hole To Hole Clearance (Gap=0.254mm) (Disabled)(All),(All) |
0 |
| Minimum Solder Mask Sliver (Gap=0.254mm) (Disabled)(All),(All) |
0 |
| Silk To Solder Mask (Clearance=0.254mm) (Disabled)(IsPad),(All) |
0 |
| Silk to Silk (Clearance=0.127mm) (Disabled)(All),(All) |
0 |
| Net Antennae (Tolerance=0mm) (All) |
0 |
| Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) |
0 |
| Total |
0 |
